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Table 19.5 Interrupt Exception Handling Sources and Priority Order (cont)
Interrupt Source
RTC
ATI
PRI
CUI
SCI1
ERI
RXI
TXI
TEI
SCIF
ERI
RXI
BRI
TXI
WDT
ITI
REF
RCMI
ROVI
Note: TUNI0–TUNI2: Underflow interrupts
TICPI2: Input capture interrupt
ATI:
Alarm interrupt
PRI:
Periodic interrupt
CUI:
Carry-up interrupt
ERI:
Receive-error interrupt
RXI:
Receive-data-full interrupt
TXI:
Transmit-data-empty interrupt
TEI:
Transmit-end interrupt
BRI:
Break interrupt request
ITI:
Interval timer interrupt
RCMI:
Compare-match interrupt
ROVI:
Refresh counter overflow interrupt
H-UDI: Hitachi use debug interface
GPIOI: I/O port interrupt
DMTE0–DMTE3: DMAC transfer end interrupts
DMAE: DMAC address error interrupt
* Interrupt priority levels can only be changed in the SH7750S. In the SH7750, the initial
values cannot be changed.
Rev. 4.0, 04/00, page 668 of 850
INTEVT
Interrupt Priority
Code
(Initial Value)
H'480
15–0 (0)
H'4A0
H'4C0
H'4E0
15–0 (0)
H'500
H'520
H'540
H'700
15–0 (0)
H'720
H'740
H'760
H'560
15–0 (0)
H'580
15–0 (0)
H'5A0
IPR (Bit
Priority within
Numbers)
IPR Setting Unit
IPRA (3–0)
High
↑
↓
Low
IPRB (7–4)
High
↑
↓
Low
IPRC (7–4)
High
↑
↓
Low
IPRB (15–12) —
IPRB (11–8)
High
Low
Default
Priority
High
↑
↓
Low
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