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17.3.2 Pin Connections ................................................................................................... 619
17.3.3 Data Format ......................................................................................................... 620
17.3.4 Register Settings .................................................................................................. 621
17.3.5 Clock.................................................................................................................... 623
17.3.6 Data Transfer Operations..................................................................................... 626
17.4 Usage Notes ...................................................................................................................... 633
18.1 Overview........................................................................................................................... 639
18.1.1 Features................................................................................................................ 639
18.1.2 Block Diagrams ................................................................................................... 640
18.1.3 Pin Configuration................................................................................................. 647
18.1.4 Register Configuration......................................................................................... 649
18.2 Register Descriptions ........................................................................................................ 650
18.2.1 Port Control Register A (PCTRA) ....................................................................... 650
18.2.2 Port Data Register A (PDTRA) ........................................................................... 651
18.2.3 Port Control Register B (PCTRB) ....................................................................... 652
18.2.4 Port Data Register B (PDTRB) ............................................................................ 653
18.2.5 GPIO Interrupt Control Register (GPIOIC) ......................................................... 653
18.2.6 Serial Port Register (SCSPTR1) .......................................................................... 654
18.2.7 Serial Port Register (SCSPTR2) .......................................................................... 656
19.1 Overview........................................................................................................................... 659
19.1.1 Features................................................................................................................ 659
19.1.2 Block Diagram..................................................................................................... 659
19.1.3 Pin Configuration................................................................................................. 661
19.1.4 Register Configuration......................................................................................... 661
19.2 Interrupt Sources............................................................................................................... 662
19.2.1 NMI Interrupt....................................................................................................... 662
19.2.2 IRL Interrupts ...................................................................................................... 663
19.2.3 On-Chip Peripheral Module Interrupts ................................................................ 665
19.2.4 Interrupt Exception Handling and Priority........................................................... 666
19.3 Register Descriptions ........................................................................................................ 669
19.3.1 Interrupt Priority Registers A to D (IPRA-IPRD) ............................................... 669
19.3.2 Interrupt Control Register (ICR).......................................................................... 670
19.4 INTC Operation ................................................................................................................ 672
19.4.1 Interrupt Operation Sequence .............................................................................. 672
19.4.2 Multiple Interrupts ............................................................................................... 674
19.4.3 Interrupt Masking with MAI Bit.......................................................................... 674
19.5 Interrupt Response Time................................................................................................... 675
Rev. 4.0, 04/00, page xviii of 20
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