Table of Contents
Advertisement
Bit 31—Endian Flag (ENDIAN): Samples the value of the endian specification external pin
(MD5) in a power-on reset. The endian mode of all spaces is determined by this bit. ENDIAN is a
read-only bit.
Bit 31: ENDIAN
0
1
Bit 30—Master/Slave Flag (MASTER): Samples the value of the master/slave specification
external pin (MD7) in a power-on reset. The master/slave status of all spaces is determined by this
bit. MASTER is a read-only bit.
Bit 30: MASTER
0
1
Bit 29—Area 0 Memory Type (A0MPX): Samples the value of the area 0 memory type
specification external pin (MD6) in a power-on reset. The memory type of area 0 is determined by
this bit. A0MPX is a read-only bit.
Bit 29: A0MPX
0
1
Bits 28 to 26, 23, 22, 16, and 1—Reserved: These bits are always read as 0, and should only be
written with 0.
Description
In a power-on reset, the endian setting external pin (MD5) is low,
designating big-endian mode for the SH7750
In a power-on reset, the endian setting external pin (MD5) is high,
designating little-endian mode for the SH7750
Description
In a power-on reset, the master/slave setting external pin (MD7) is low,
designating master mode for the SH7750
In a power-on reset, the master/slave setting external pin (MD7) is high,
designating slave mode for the SH7750
Description
In a power-on reset, the external pin specifying the area 0 memory type
(MD6) is low, designating the area 0 as SRAM interface
In a power-on reset, the external pin specifying the area 0 memory type
(MD6) is high, designating the area 0 as MPX interface
Rev. 4.0, 04/00, page 273 of 850
Advertisement
Table of Contents
