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Table 19.6 Interrupt Request Sources and IPRA–IPRD Registers
Register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D*
Notes: 1. REF is the memory refresh unit in the bus state controller (BSC). See section 13, Bus
State Controller (BSC), for details.
2. Reserved bits: These bits are always read as 0 and should always be written with 0.
3. SH7750S only
As shown in table 19.6, four on-chip peripheral modules are assigned to each register. Interrupt
priority levels are established by setting a value from H'F (1111) to H'0 (0000) in each of the four-
bit groups: 15–12, 11–8, 7–4, and 3–0. Setting H'F designates priority level 15 (the highest level),
and setting H'0 designates priority level 0 (requests are masked).
19.3.2
Interrupt Control Register (ICR)
The interrupt control register (ICR) is a 16-bit register that sets the input signal detection mode for
external interrupt input pin NMI and indicates the input signal level at the NMI pin. This register
is initialized by a power-on reset or manual reset. It is not initialized in standby mode.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Note: * 1 when NMI pin input is high, 0 when low.
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. It cannot be modified.
Rev. 4.0, 04/00, page 670 of 850
15–12
TMU0
WDT
GPIO
3
IRL0
15
14
NMIL
MAI
0/1*
0
R
R/W
7
6
IRLM
—
0
0
R/W
—
11–8
TMU1
1
REF*
DMAC
IRL1
13
12
—
—
0
0
—
—
5
4
—
—
0
0
—
—
Bits
7–4
3–0
TMU2
RTC
SCI1
Reserved*
SCIF
H-UDI
IRL2
IRL3
11
10
—
—
NMIB
0
0
—
—
R/W
3
2
—
—
0
0
—
—
2
9
8
NMIE
0
0
R/W
1
0
—
—
0
0
—
—
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