Hitachi SH7750 series Hardware Manual page 735

Table 22.2 Pin Functions (cont)
Pin
No. Pin Name
:(7/&$67/
59
DQM4
:(4/&$64/
60
DQM1
:(3/&$63/
61
DQM0
62 A17
63 A16
64 A15
65 VDD
66 VSS
67 A14
68 A13
69 VDDQ
70 VSSQ
71 A12
72 A11
73 A10
74 A9
75 A8
76 A7
77 CKIO
78 VDDQ
79 VSSQ
80 A6
81 A5
82 A4
83 A3
84 A2
85 DRAK1
86 DRAK0
87 VDDQ
I/O Function
O D39–D32 select
signal
O D15–D8 select
signal
O D7–D0 select
signal
O Address
O Address
O Address
Power Internal VDD
(1.8 V)
Power Internal GND
(0 V)
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O Address
O Address
O Address
O Address
O Clock output
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O Address
O Address
O Address
O DMAC1 request
acknowledge
O DMAC0 request
acknowledge
Power IO VDD (3.3 V)
SRAM DRAM
Reset
:(7 &$67
:(4 &$64
:(3 &$63
Memory Interface
SDRAM PCMCIA MPX
DQM4
:(4
DQM1
DQM0
CKIO
Rev. 4.0, 04/00, page 727 of 850