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memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in
the transfer to external memory is deferred until the transfer is completed.
The SQ transfer destination external memory address bit [28:0] specification is as shown below,
according to whether the MMU is on or off.
• When MMU is on
The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer
destination external memory address in PPN. The ASID, V, SZ, SH, PR, and D bits have the
same meaning as for normal address translation, but the C and WT bits have no meaning with
regard to this page. Since burst transfer is prohibited for PCMCIA areas, the SA and TC bits
also have no meaning.
When a prefetch instruction is issued for the SQ area, address translation is performed and
external memory address bits [28:10] are generated in accordance with the SZ bit specification.
For external memory address bits [9:5], the address prior to address translation is generated in
the same way as when the MMU is off. External memory address bits [4:0] are fixed at 0.
Transfer from the SQs to external memory is performed to this address.
• When MMU is off
The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address at which a prefetch is
performed. The meaning of address bits [31:0] is as follows:
[31:26]:
111000
[25:6]:
Address
[5]:
0/1
[4:2]:
Don't care
[1:0]
00
External memory address bits [28:26], which cannot be generated from the above address, are
generated from the QACR0/1 registers.
QACR0 [4:2]:
QACR1 [4:2]:
External memory address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte
boundary.
Rev. 4.0, 04/00, page 80 of 850
Store queue specification
External memory address bits [25:6]
0: SQ0 specification
1: SQ1 specification and external memory address bit [5]
No meaning in a prefetch
Fixed at 0
External memory address bits [28:26] corresponding to SQ0
External memory address bits [28:26] corresponding to SQ1
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