Hitachi SH7750 series Hardware Manual page 367

Superh risc engine

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Burst Write: The timing chart for a burst write is shown in figure 13.28. In the SH7750, a burst

write occurs only in the event of cache copy-back or a 32-byte transfer by the DMAC. In a burst

write operation, the WRIT command is issued in the Tc1 cycle following the Tr cycle in which the

ACTV command is output and, 4 cycles later, the WRITA command is issued. In the write cycle,

the write data is output at the same time as the write command. In the case of the write with auto-

precharge command, precharging of the relevant bank is performed in the synchronous DRAM

after completion of the write command, and therefore no command can be issued for the same

bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc,

used in a read access, cycle Trwl is also added as a wait interval until precharging is started

following the write command. Issuance of a new command for the same bank is postponed during

this interval. The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR.

Access starts from 16-byte boundary data, and 32-byte boundary data is written in wraparound

Precharge-sel

(SA: IO → memory)

Figure 13.28 Basic Timing for Synchronous DRAM Burst Write

Rev. 4.0, 04/00, page 356 of 850

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