Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment
Operation
Access
Size
Address No. D31–D24 D23–D16 D15–D8 D7–D0
Byte
2n
1
2n+1
1
Word
2n
1
Long-
4n
1
word
4n+2
2
Quad-
8n
1
word
8n+2
2
8n+4
3
8n+6
4
Rev. 4.0, 04/00, page 318 of 850
Data Bus
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
:(6
:(6,
:(6
:(6
&$66
&$66,
&$66
&$66
DQM3
—
Data
7–0
Data
—
7–0
Data
Data
15–8
7–0
Data
Data
15–8
7–0
Data
Data
31–24
23–16
Data
Data
15–8
7–0
Data
Data
31–24
23–16
Data
Data
47–40
39–32
Data
Data
63–56
55–48
Strobe Signals
:(5,
:(5
:(4
:(4,
:(3,
:(3
:(5
:(5
:(4
:(4
:(3
:(3
&$65,
&$65
&$64,
&$64
&$63,
&$63
&$65
&$65
&$64
&$64
&$63
&$63
DQM2
DQM1
DQM0
Asserted
Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted