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1. Page table entry high register (PTEH): Longword access to PTEH can be performed from
H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number
(VPN) and address space identifier (ASID). When an MMU exception or address error exception
occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by
hardware. VPN varies according to the page size, but the VPN set by hardware when an exception
occurs consists of the upper 22 bits of the virtual address which caused the exception. VPN setting
can also be carried out by software. The number of the currently executing process is set in the
ASID field by software. ASID is not updated by hardware. VPN and ASID are recorded in the
UTLB by means of the LDLTB instruction.
2. Page table entry low register (PTEL): Longword access to PTEL can be performed from
H'FF00 0004 in the P4 area and H'1F00 0004 in area 7. PTEL is used to hold the physical page
number and page management information to be recorded in the UTLB by means of the LDTLB
instruction. The contents of this register are not changed unless a software directive is issued.
3. Page table entry assistance register (PTEA): Longword access to PTEA can be performed
from H'FF00 0034 in the P4 area and H'1F00 0034 in area 7. PTEL is used to store assistance bits
for PCMCIA access to the UTLB by means of the LDTLB instruction. When performing
PCMCIA access in the SH7750S with the MMU off, access is always performed using the values
of the SA and TC bits in this register. In the SH7750, PCMCIA access cannot be performed with
the MMU off. The contents of this register are not changed unless a software directive is issued.
4. Translation table base register (TTB): Longword access to TTB can be performed from
H'FF00 0008 in the P4 area and H'1F00 0008 in area 7. TTB is used, for example, to hold the base
address of the currently used page table. The contents of TTB are not changed unless a software
directive is issued. This register can be freely used by software.
5. TLB exception address register (TEA): Longword access to TEA can be performed from
H'FF00 000C in the P4 area and H'1F00 000C in area 7. After an MMU exception or address error
exception occurs, the virtual address at which the exception occurred is set in TEA by hardware.
The contents of this register can be changed by software.
6. MMU control register (MMUCR): MMUCR contains the following bits:
LRUI: Least recently used ITLB
URB:
UTLB replace boundary
URC:
UTLB replace counter
SQMD: Store queue mode bit
SV:
Single virtual mode bit
TI:
TLB invalidate
AT:
Address translation bit
Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00
0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR
rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an
Rev. 4.0, 04/00, page 30 of 850
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