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e. In the case of an RTE delay slot
The BL bit value before execution of a delay slot instruction is the same as the BL bit value
before execution of an RTE instruction. The BL bit value after execution of a delay slot
instruction is the same as the first BL bit value for the first instruction executed on
returning by means of an RTE instruction (the same as the value of the BL bit in SSR
before execution of the RTE instruction).
f. If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit
before execution of the first instruction of the exception handling routine is 1.
4. If channels A and B both match independently at virtually the same time, and, as a result, the
SPC value is the same for both user break interrupts, only one user break interrupt is generated,
but both the CMFA bit and the CMFB bit are set. For example:
110 Instruction (post-execution instruction break on channel A) → SPC = 112, CMFA = 1
112 Instruction (pre-execution instruction break on channel B) → SPC = 112, CMFB = 1
5. The PCBA or PCBB bit in BRCR is invalid for an instruction access break setting.
6. When the SEQ bit in BRCR is 1, the internal sequential break state is initialized by a channel
B condition match. For example: A → A → B (user break generated) → B (no break
generated)
7. In the event of contention between a re-execution type exception and a post-execution break in
a multistep instruction, the re-execution type exception is generated. In this case, the CMF bit
may or may not be set to 1 when the break condition occurs.
8. A post-execution break is classified as a completion type exception. Consequently, in the event
of contention between a completion type exception and a post-execution break, the post-
execution break is suppressed in accordance with the priorities of the two events. For example,
in the case of contention between a TRAPA instruction and a post-execution break, the user
break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break
condition.
20.4
User Break Debug Support Function
The user break debug support function enables the processing used in the event of a user break
exception to be changed. When a user break exception occurs, if the UBDE bit is set to 1 in the
BRCR register, the DBR register value will be used as the branch destination address instead of
[VBR + offset]. The value of R15 is saved in the SGR register regardless of the value of the
UBDE bit in the BRCR register or the kind of exception event. A flowchart of the user break
debug support function is shown in figure 20.2.
Rev. 4.0, 04/00, page 697 of 850
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