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The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues
(SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the
MMUCR.SQMD bit. For details, see section 4.6, Store Queues.
The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache
address array. For details, see section 4.5.1, IC Address Array.
The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data
array. For details, see section 4.5.2, IC Data Array.
The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB
address array. For details, see section 3.7.1, ITLB Address Array.
The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data
arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2.
Rev. 4.0, 04/00, page 34 of 850
H'E000 0000
H'E400 0000
H'F000 0000
Instruction cache address array
H'F100 0000
H'F200 0000
H'F300 0000
Instruction TLB data arrays 1 and 2
H'F400 0000
H'F500 0000
H'F600 0000
H'F700 0000
Unified TLB data arrays 1 and 2
H'F800 0000
H'FF00 0000
Figure 3.4 P4 Area
Store queue
Reserved area
Instruction cache data array
Instruction TLB address array
Operand cache address array
Operand cache data array
Unified TLB address array
Reserved area
Control register area
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