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21.1.4
Register Configuration
Table 21.2 shows the H-UDI registers. Except for SDBPR, these registers are mapped in the
control register space and can be referenced by the CPU.
Table 21.2 H-UDI Registers
Abbre-
Name
viation
Instruction
SDIR
register
Data register
SDDR/
H
SDDRH
Data register
SDDRL R/W H'FFF0000A H'1FF0000A 16
L
Bypass
SDBPR —
register
Notes: 1. Initialized when the 7567 pin goes low or when the TAP is in the Test-Logic-Reset
state.
2. The value read from H-UDI is fixed (H'FFFFFFFD).
Rev. 4.0, 04/00, page 706 of 850
CPU Side
P4
Area 7
R/W
Address
Address
R
H'FFF00000 H'1FF00000 16
R/W H'FFF00008 H'1FF00008 32/16
—
—
Access
Initial
1
Size
Value*
R/W
H'FFFF
R/W
Unde-
—
fined
Unde-
—
fined
—
Unde-
R/W
fined
H-UDI Side
Access
Initial
1
Size
Value*
32
H'FFFFFFFD
(Fixed
2
value*
)
—
—
—
—
1
—
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