Hitachi SH7750 series Hardware Manual page 245

Superh risc engine
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Bit 2—30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this
bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is
rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also
reset at this time. This bit always returns 0 if read.
Bit 2: ADJ
0
1
Bit 1—Reset (RESET): The frequency divider circuits are initialized by writing 1 to this bit.
When 1 is written to the RESET bit, the frequency divider circuits (RTC prescaler and R64CNT)
are reset and the RESET bit is automatically cleared to 0 (i.e. does not need to be written with 0).
Bit 1: RESET
0
1
Bit 0—Start Bit (START): Stops and restarts counter (clock) operation.
Bit 0: START
0
1
Note: * The 64 Hz counter continues to operate unless stopped by means of the RTCEN bit.
Description
Normal clock operation
30-second adjustment performed
Description
Normal clock operation
Frequency divider circuits are reset
Description
Second, minute, hour, day, day-of-week, month, and year counters are
stopped*
Second, minute, hour, day, day-of-week, month, and year counters operate
normally*
(Initial value)
(Initial value)
(Initial value)
Rev. 4.0, 04/00, page 233 of 850

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