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When software wait insertion is specified by WCR2, the external wait input 5'< signal is also
sampled. 5'< signal sampling is shown in figure 13.11. A single-cycle wait is specified as a
software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore,
the 5'< signal has no effect if asserted in the T1 cycle or the first Tw cycle. The 5'< signal is
sampled on the rising edge of the clock.
CKIO
A25–A0
RD/
(read)
D63–D0
(read)
(write)
D63–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Figure 13.11 Basic Interface Wait State Timing (Wait State Insertion by 5'<
T1
Tw
Twe
T2
Rev. 4.0, 04/00, page 331 of 850
5'< Signal)
5'<
5'<
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