Hitachi SH7750 series Hardware Manual page 777

CKIO
BANK
Precharge-sel
Addr
RD/
DQMn
D63–D0
(read)
D63–D0
(write)
CKE
DACKn
(SA: IO ← memory)
Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,
Tr Trw Tc1
t
AD
Row
t
t
AD
RWD
Row H/L
t
RWD
Row c0
t
CSD
t
RWD
t
t
RASD
RASD
t t
CASD2 CASD2
t
DQMD
t
WDD
t
DACD
Burst (RCD = 1, CAS Latency = 3)
Tc2 Tc3 Tc4/Td1
t
CASD2
t
RDS
t
BSD
t
DACD
Td3 Td4
Td2
t
DQMD
t
RDH
d0 d1 d2
t
BSD
Rev. 4.0, 04/00, page 769 of 850
t
AD
t
CSD
t
RWD
d3
t
WDD
t
DACD