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Bit 21: TPC2
0
1
Note: * Inhibited in RAS down mode.
Bits 17 and 16—RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits
set the 5$6-&$6 assertion delay time. When the synchronous DRAM interface is set, these bits
set the bank active-read/write command delay time.
Bit 17: RCD1
0
1
Note: * Inhibited in RAS down mode.
Bits 15 to 13—Write Precharge Delay (TRWL2–TRWL0): These bits set the synchronous
DRAM write precharge delay time. In auto-precharge mode, they specify the time until the next
bank active command is issued after a write cycle. After a write cycle, the next active command is
not issued for a period of TPC + TRWL. In RAS down mode, they specify the time until the next
precharge command is issued. After a write cycle, the next precharge command is not issued for a
period of TRWL. This setting is valid only when synchronous DRAM interface is set.
Bit 20: TPC1
0
1
0
1
Bit 16: RCD0
0
1
0
1
Bit 19: TPC0
0
1
0
1
0
1
0
1
DRAM
2 cycles
3 cycles
4 cycles
5 cycles
RAS Precharge Interval
DRAM
Synchronous DRAM
0
1* (Initial value)
1
2
2
3
3
4*
4
5*
5
6*
6
7*
7
8*
Description
Synchronous DRAM
Reserved (Setting prohibited)
2 cycles
3 cycles
4 cycles*
Rev. 4.0, 04/00, page 295 of 850
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