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instruction that performs data access to the P0, P3, U0, or store queue area should be located at
least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0,
P3, or U0 area should be located at least eight instructions after the MMUCR update instruction.
MMUCR contents can be changed by software. The LRUI bits and URC bits may also be updated
by hardware.
• LRUI: The LRU (least recently used) method is used to decide the ITLB entry to be replaced
in the event of an ITLB miss. The entry to be purged from the ITLB can be confirmed using
the LRUI bits. LRUI is updated by means of the algorithm shown below. A dash in this table
means that updating is not performed.
When ITLB entry 0 is used
When ITLB entry 1 is used
When ITLB entry 2 is used
When ITLB entry 3 is used
Other than the above
When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by
an ITLB miss. An asterisk in this table means "don't care".
ITLB entry 0 is updated
ITLB entry 1 is updated
ITLB entry 2 is updated
ITLB entry 3 is updated
Other than the above
Ensure that values for which "Setting prohibited" is indicated in the above table are not set at
the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0,
and therefore a prohibited setting is never made by a hardware update.
• URB: Bits that indicate the UTLB entry boundary at which replacement is to be performed.
Valid only when URB > 0.
• URC: Random counter for indicating the UTLB entry for which replacement is to be
performed with an LDTLB instruction. URC is incremented each time the UTLB is accessed.
When URB > 0, URC is reset to 0 when the condition URC = URB occurs. Also note that, if a
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Setting prohibited
LRUI
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LRUI
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*
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Rev. 4.0, 04/00, page 31 of 850
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