Hitachi SH7750 series Hardware Manual page 348

Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in
figure 13.15. Tpc is the precharge cycle, Tr the 5$6 assert cycle, Tc1 the &$6 assert cycle, and
Tc2 the read data latch cycle.
CKIO
A25–A0
RD/
D63–D0
(read)
D63–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Tr1 Tr2
Row
Figure 13.15 Basic DRAM Access Timing
Tc1 Tc2
Column
Rev. 4.0, 04/00, page 337 of 850
Tpc