Hitachi SH7750 series Hardware Manual page 369

Superh risc engine
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CKIO
Bank
Precharge-sel
Address
RD/
DQMn
D63–D0
(read)
CKE
DACKn
(SA: IO → memory)
Figure 13.29 Basic Timing for Synchronous DRAM Single Write
Rev. 4.0, 04/00, page 358 of 850
Tr
Trw
Tc1
Row
Row
Row
c1
Tc2
Tc3
Tc4
H/L
c1
Trw1
Trw1
Tpc

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