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13.3.2
Areas
Area 0: For area 0, external address bits A28 to A26 are 000.
SRAM, MPX, and burst ROM can be set to this area.
A bus width of 8, 16, 32, or 64 bits can be selected in a power-on reset by means of external pins
MD4 and MD3. For details, see Memory Bus Width in section 13.1.5.
When area 0 is accessed, the &63 signal is asserted. In addition, the 5' signal, which can be used
as 2(, and write control signals :(3 to :(:, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A0W2 to A0W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (5'<).
When the burst ROM interface is used, the number of burst cycle transfer states is selected in the
range 2 to 9 according to the number of waits.
Area 1: For area 1, external address bits A28 to A26 are 001.
SRAM and MPX can be set to this area.
A bus width of 8, 16, 32, or 64 bits can be selected with bits A1SZ1 and A1SZ0 in the BCR2
register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits
A1SZ1 and A1SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus
width of 16, 32, or 64 bits.
When area 1 is accessed, the &64 signal is asserted. In addition, the 5' signal, which can be used
as 2(, and write control signals :(3 to :(:, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A1W2 to A1W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (5'<).
The read/write strobe signal address and &6 setup and hold times can be set within a range of 0–1
and 0–3 cycles, respectively, by means of bit A1S0 and bits A1H1 and A1H0 in the WCR3
register.
Area 2: For area 2, external address bits A28 to A26 are 010.
SRAM, MPX, and synchronous DRAM can be set to this area.
When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A2SZ1
and A2SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should
be selected with bits A2SZ1 and A2SZ0 in the BCR2 register. When synchronous DRAM
Rev. 4.0, 04/00, page 320 of 850
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