Block Diagram; Pin Configuration - Hitachi SH7750 series Hardware Manual

12.1.2

Block Diagram

Figure 12.1 shows a block diagram of the TMU.
RESET, STBY, TUNI0
etc.
TMU
control unit
Ch 0
Interrupt
Counter unit
control unit
TCR0 TCOR0
Note: * Signals with 1/4, 1/16, and 1/64 the Pφ frequency, supplied to the on-chip peripheral functions.
12.1.3

Pin Configuration

Table 12.1 shows the TMU pins.
Table 12.1 TMU Pins
Pin Name
Clock input/clock output
Rev. 4.0, 04/00, page 242 of 850
PCLK/4, 16, 64*
Prescaler
To each
channel
Ch 1
Counter unit
TCNT0 TCR1 TCOR1
Bus interface
Figure 12.1 Block Diagram of TMU
Abbreviation
TCLK
TUNI1 TCLK RTCCLK
TCLK
control unit
To each
channel
Ch 2
Interrupt
Counter unit
control unit
TCNT1 TCR2
Internal peripheral module bus
I/O Function
I/O External clock input pin/input capture
control input pin/RTC output pin
(shared with RTC)
TUNI2 TICPI2
Interrupt
control unit
TCOR2 TCNT2 TCPR2
TOCR
TSTR