Hitachi SH7750 series Hardware Manual page 786

TRr1
CKIO
t
AD
BANK
Precharge-sel
Addr
t
CSD
t
RWD
RD/
t
RASD
t
CASD2
t
DQMD
DQMn
t
WDD
D63–D0
(write)
CKE
t
DACD
DACKn
Figure 23.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh
Rev. 4.0, 04/00, page 778 of 850
TRr2 TRr3 TRr4
t t
CSD CSD
t t
RASD RASD
t t
CASD2 CASD2
(TRAS = 1, TRC = 1)
TRrw TRr5 Trc
Trc Trc
t
AD
t
CSD
t
RWD
t
RASD
t
CASD2
t
DQMD
t
WDD
t
BSD
t
DACD