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When the input clock is the on-chip RTC output clock (RTCCLK), TCNT counts even in module
standby mode (that is, when the clock for the TMU is stopped). When the input clock is the
external clock (TCLK) or internal clock (Pφ), TCNT contents are retained in standby mode.
12.2.5
Timer Control Registers (TCR)
The TCR registers are 16-bit readable/writable registers. There are three TCR registers, one for
each channel.
Each TCR selects the count clock, specifies the edge when an external clock is selected, and
controls interrupt generation when the flag indicating timer counter (TCNT) underflow is set to 1.
TCR2 is also used for channel 2 input capture control, and control of interrupt generation in the
event of input capture.
The TCR registers are initialized to H'0000 by a power-on or manual reset, but are not initialized
in standby mode.
1. Channel 0 and 1 TCR bit configuration
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
2. Channel 2 TCR bit configuration
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
15
14
—
—
0
0
R
R
7
6
—
—
0
0
R
R
15
14
—
—
0
0
R
R
7
6
ICPE1
ICPE0
0
0
R/W
R/W
13
12
—
—
0
0
R
R
5
4
UNIE
CKEG1 CKEG0
0
0
R/W
R/W
13
12
—
—
0
0
R
R
5
4
UNIE
CKEG1 CKEG0
0
0
R/W
R/W
11
10
—
—
0
0
R
R
3
2
TPSC2
TPSC1
0
0
R/W
R/W
11
10
—
—
ICPF
0
0
R
R/W
3
2
TPSC2
TPSC1
0
0
R/W
R/W
Rev. 4.0, 04/00, page 247 of 850
9
8
—
UNF
0
0
R
R/W
1
0
TPSC0
0
0
R/W
R/W
9
8
UNF
0
0
R/W
R/W
1
0
TPSC0
0
0
R/W
R/W
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