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Table 13.1 BSC Pins (cont)
Name
Data enable 6
Data enable 7
Ready
Area 0 MPX
interface
specification/
16-bit I/O
Clock enable
Bus release
request
Bus use
permission
Area 0 bus
width/PCMCIA
card select
Endian switchover/
row address strobe
Master/slave
switchover
DMAC0
acknowledge
signal
DMAC1
acknowledge
signal
Rev. 4.0, 04/00, page 262 of 850
Signals
I/O
:(9/&$69/
O
DQM6
:(:/&$6:/
O
DQM7/5(*
5'<
I
MD6/,2,649
I
CKE
O
%5(4/
I
%6$&.
%$&./
O
%65(4
1
MD3/&(5$*
I/O
2
MD4/&(5%*
3
MD5/5$65*
I/O
MD7/TXD
I/O
DACK0
O
DACK1
O
Description
When setting synchronous DRAM interface:
selection signal for D55–D48
When setting DRAM interface: &$6 signal for
D55–D48
When setting MPX interface: high-level output
In other cases: write strobe signal for D55–D48
When setting synchronous DRAM interface:
selection signal for D63–D56
When setting DRAM interface: &$6 signal for
D63–D56
When setting PCMCIA interface: 5(* signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D63–D56
Wait state request signal
In power-on reset: Designates area 0 bus as MPX
interface (1: SRAM, 0: MPX)
When setting PCMCIA interface: 16-bit I/O
designation signal. Valid only in little-endian mode.
Synchronous DRAM clock enable control signal
Bus release request signal/bus acknowledge signal
Bus use permission signal/bus request
In power-on reset: external space area 0 bus width
specification signal
When setting PCMCIA interface: &(5$, &(5%
Endian specification in a power-on reset.
5$65 when DRAM is connected to area 2
Indicates master/slave status in a power-on reset.
Serial interface TXD
DMAC channel 0 data acknowledge
DMAC channel 1 data acknowledge
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