Hitachi SH7750 series Hardware Manual page 707

Superh risc engine
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Hardware operation
EXPEVT ← exception code
Yes
PC ← DBR
Debug program
R15 ← SGR
(STC instruction)
Figure 20.2 User Break Debug Support Function Flowchart
Rev. 4.0, 04/00, page 698 of 850
Exception
No
(BRCR.UBDE == 1) &&
(user break exception)?
Exception/interrupt
generation
SPC ← PC
SSR ← SR
SR.BL ← B'1
SR.MD ← B'1
SR.RB ← B'1
Exception/
interrupt/trap?
Interrupt
INTEVT ← interrupt code
SGR ← R15
Reset exception?
No
PC ← VBR + vector offset
Exception handler
Execute RTE instruction
PC ← SPC
SR ← SSR
End of exception
operations
Trap
TRA ← TRAPA (imm)
Yes
PC ← H'A0000000

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