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Start of transmission
Read TDRE flag in SCSSR1
TDRE = 1?
Yes
Write transmit data to SCTDR1
and clear TDRE flag
in SCSSR1 to 0
All data transmitted?
Yes
Read TEND flag in SCSSR1
TEND = 1?
Yes
Break output?
Yes
Clear SPB0DT to 0 and
set SPB0IO to 1
Clear TE bit in SCSCR1 to 0
End of transmission
Figure 15.8 Sample Serial Transmission Flowchart
1. SCI status check and transmit data
write: Read SCSSR1 and check that
the TDRE flag is set to 1, then write
transmit data to SCTDR1 and clear
the TDRE flag to 0.
2. Serial transmission continuation
No
procedure: To continue serial
transmission, read 1 from the TDRE
flag to confirm that writing is possible,
then write data to SCTDR1, and then
clear the TDRE flag to 0. (Checking
and clearing of the TDRE flag is
automatic when the direct memory
access controller (DMAC) is activated
by a transmit-data-empty interrupt
No
(TXI) request, and data is written to
SCTDR1.)
3. Break output at the end of serial
transmission: To output a break in
serial transmission, clear the SPB0DT
bit to 0 and set the SPB0IO bit to 1 in
SCSPTR, then clear the TE bit in
SCSCR1 to 0.
No
No
Rev. 4.0, 04/00, page 537 of 850
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