Register Descriptions; Smart Card Mode Register (Scscmr1) - Hitachi SH7750 series Hardware Manual

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Register Descriptions

Only registers that have been added, and bit functions that have been modified, for the smart card

interface are described here.

SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function.

SCSCMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the

module standby state.

Initial value:

Bits 7 to 4 and 1—Reserved: These bits are always read as 0, and should only be written with 0.

Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion

Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This

function is used together with the bit 3 function for communication with an inverse convention

card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting

procedures, see section 17.3.4, Register Settings.

Rev. 4.0, 04/00, page 614 of 850

SCTDR1 contents are transmitted LSB-first

Receive data is stored in SCRDR1 LSB-first

SCTDR1 contents are transmitted MSB-first

Receive data is stored in SCRDR1 MSB-first

SCTDR1 contents are transmitted as they are

Receive data is stored in SCRDR1 as it is

SCTDR1 contents are inverted before being transmitted

Receive data is stored in SCRDR1 in inverted form

(Initial value)

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