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14.6
Usage Notes
1. When modifying SAR0–SAR3, DAR0–DAR3, DMATCR0–DMATCR3, and CHCR0–
CHCR3, first clear the DE bit for the relevant channel to 0.
2. The NMIF bit in DMAOR is set when an NMI interrupt is input even if the DMAC is not
operating.
Confirmation method when DMA transfer is not executed correctly:
Read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0–CHCR3, and
DMATCR0–DMATCR3. If NMIF was set before the transfer, the DMATCR transfer count
will remain at the set value. If NMIF was set during the transfer, when the DE bit is 1 and the
TE bit is 0 in CHCR0–CHCR3, the DMATCR value will indicate the remaining number of
transfers.
Also, the next addresses to be accessed can be found by reading SAR0–SAR3 and DAR0–
DAR3. If the AE bit has been set, an address error has occurred. Check the set values in
CHCR, SAR, and DAR.
3. Check that DMA transfer is not in progress before making a transition to the module standby
state, standby mode, or deep sleep mode.
Either check that TE = 1 in CHCR0–CHCR3, or clear DME to 0 in DMAOR to terminate
DMA transfer. When DME is cleared to 0 in DMAOR, transfer halts at the end of the currently
executing DMA bus cycle. Note, therefore, that transfer may not end immediately, depending
on the transfer data size. DMA operation is not guaranteed if the module standby state, standby
mode, or deep sleep mode is entered without confirming that DMA transfer has ended.
4. Do not specify a DMAC, CCN, BIST, BSC, or UBC control register as the DMAC transfer
source or destination.
5. When activating the DMAC, make the SAR, DAR, and DMATCR register settings for the
relevant channel before setting DE to 1 in CHCR, or make the register settings with DE
cleared to 0 in CHCR, then set DE to 1. It does not matter whether setting of the DME bit to 1
in DMAOR is carried out first or last. To operate the relevant channel, DME and DE must both
be set to 1. The DMAC may not operate normally if the SAR, DAR, and DMATCR settings
are not made (with the exception of the unused register in single address mode).
6. After the DMATCR count reaches 0 and DMA transfer ends normally, always write 0 to
DMATCR even when executing the maximum number of transfers on the same channel.
7. When falling edge detection is used for external requests, keep the external request pin high
when making DMAC settings.
8. When using the DMAC in single address mode, set an external address as the address. All
channels will halt due to an address error if an on-chip peripheral module address is set.
Rev. 4.0, 04/00, page 502 of 850
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