Hitachi SH7750 series Hardware Manual page 575

When Using the DMAC: When an external clock source is used as the serial clock, the transmit
clock should not be input until at least 5 peripheral operating clock cycles after SCTDR1 is
updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 cycles
after SCTDR1 is updated. (See figure 15.25)
SCK
t
TDRE
TxD
Note: When operating on an external clock, set t > 4.
Figure 15.25 Example of Synchronous Transmission by DMAC
When SCRDR1 is read by the DMAC, be sure to set the SCI receive-data-full interrupt (RXI) as
the activation source with bits RS3 to RS0 in CHCR.
• When using the DMAC for transmission/reception, making a setting to disable RXI and TXI
interrupt requests to the interrupt controller. Even if issuance of interrupt requests is set,
interrupt requests to the interrupt controller will be cleared by the DMAC independently of the
interrupt handling program.
When Using Synchronous External Clock Mode:
• Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock
SCK has changed from 0 to 1.
• Only set both TE and RE to 1 when external clock SCK is 1.
• In reception, note that if RE is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles
after the rising edge of the RxD D7 bit SCK input, RDRF will be set to 1 but copying to
SCRDR1 will not be possible.
When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero
1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDRF
will be set to 1 but copying to SCRDR1 will not be possible.
When Using DMAC: When using the DMAC for transmission/reception, make a setting to
suppress output of RXI and TXI interrupt requests to the interrupt controller. Even if a setting is
made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by
the DMAC independently of the interrupt handling program.
Rev. 4.0, 04/00, page 564 of 850
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