Hitachi SH7750 series Hardware Manual page 420

Superh risc engine
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T1
Tw
Twe
T2
CKIO
A25–A0
RD/
D63–D0
(read)
DACKn
(SA: IO ← memory)
DACKn
(DA)
Figure 13.71 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External
Wait)
Rev. 4.0, 04/00, page 409 of 850

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