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CKIO
A[25-0],
,
,
RD/
,
,
,
RD/
,
,
,
,
Normal operation
CKIO
STATUS 0, STATUS 1
CSn, RD, RD/WR,
WEn, BS, RAS, RAS2,
CE2A, CE2B, RD2,
RD/WR2
A25–A0, D63–D0
DACKn, DRAKn, SCK,
TXD, TXD2, CTS2,
*
RTS2
Note: * When the PHZ bit in STBCR is set to 1, these pins go to the high-impedance state (except
for pins being used as port pins, which retain their port state).
Rev. 4.0, 04/00, page 756 of 850
t
t
BREQS
BREQH
Figure 23.13 Control Signal Timing
Normal
t
STD2
Figure 23.14 Pin Drive Timing for Standby Mode
t
t
BREQS
BREQH
t
t
BACKH
BACKH
t
BOFF1
Standby mode
Standby
t
BOFF2
t
BON1
Normal operation
Normal
t
STD1
t
BON2
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