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write-through method is indicated by the TLB write-through bit (WT bit), and is specified in page
units.
Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the
TLB, addresses H'1F00 0000 to H'1FFF FFFF of area 7 in external memory space are allocated to
the control register area. This enables on-chip peripheral module control registers to be accessed
from the U0 area in user mode. In this case, the C bit for the corresponding page must be cleared
to 0.
In the cache enabled state, when areas P0, P3, and U0 are mapped onto the PCMCIA space by
means of TLB, it is necessary either to specify 1 for the WT bit or to specify 0 for the C bit; it is
not possible to use copy-back mode cache for the PCMCIA space.
P1, P2, P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or P4
area (except for the store queue area). Accesses to these areas are the same as for physical memory
space. The store queue area can be mapped onto any external memory space by the MMU.
However, operation in the case of an exception differs from that for normal P0, U0, and P3 spaces.
For details, see section 4.6, Store Queues.
3.3.4
On-Chip RAM Space
In the SH7750 Series, half (8 kbytes) of the instruction cache (16 kbytes) can be used as on-chip
RAM. This can be done by changing the CCR settings.
When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0 area addresses H'7C00
0000 to H'7FFF FFFF are an on-chip RAM area. Data accesses (byte/word/longword/quadword)
can be used in this area. This area can only be used in RAM mode.
3.3.5
Address Translation
When the MMU is used, the virtual address space is divided into units called pages, and
translation to physical addresses is carried out in these page units. The address translation table in
external memory contains the physical addresses corresponding to virtual addresses and additional
information such as memory protection codes. Fast address translation is achieved by caching the
contents of the address translation table located in external memory into the TLB. In the SH7750
Series, basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the
event of an access to an area other than the P4 area, the accessed virtual address is translated to a
physical address. If the virtual address belongs to the P1 or P2 area, the physical address is
uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3
area, the TLB is searched using the virtual address, and if the virtual address is recorded in the
TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the
accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and
processing switches to the TLB miss exception routine. In the TLB miss exception routine, the
Rev. 4.0, 04/00, page 37 of 850
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