Dma Destination Address Registers 0-3 (Dar0-Dar3) - Hitachi SH7750 series Hardware Manual

14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that
specify the destination address of a DMA transfer. These registers have a counter feedback
function, and during a DMA transfer they indicate the next destination address. In single address
mode, the DAR value is ignored when a device with DACK has been specified as the transfer
destination.
Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64-
bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will
be detected and the DMAC will halt.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode and deep sleep mode.
When transfer is performed from an external device to memory in DDT mode, DTR format [31:0]
is set in DAR0 [31:0].
Note: When a 16-bit, 32-bit, 64-bit, or 32-byte boundary address is specified, take care with the
setting of bit 0, bits 1–0, bits 2–0, or bits 4–0, respectively. If an address specification that
ignores boundary considerations is made, the DMAC will detect an address error and halt
operation on all channels (DMAOR: address error flag AE = 1). The DMAC will also
detect an address error and halt if an area 7 address is specified in an external data bus
transfer, or if the address of a nonexistent on-chip peripheral module is specified.
External addresses are 29-bit. As SAR[31:29] and DAR[31:29] are not used in DMA
transfers, settings of SAR[31:29] = 000 and DAR[31:29] = 000 are recommended.
Rev. 4.0, 04/00, page 426 of 850
31 30
— —
R/W R/W
23
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— · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·
R/W · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·
29 28
— —
R/W R/W
27 26
— —
R/W R/W
25 24
— —
R/W R/W
0
—
R/W