Hitachi SH7750 series Hardware Manual page 350

Superh risc engine

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Burst Access: In addition to the normal DRAM access mode in which a row address is output in

each data access, a fast page mode is also provided for the case where consecutive accesses are

made to the same row. This mode allows fast access to data by outputting the row address only

once, then changing only the column address for each subsequent access. Normal access or burst

access using fast page mode can be selected by means of the burst enable (BE) bit in MCR. The

timing for burst access using fast page mode is shown in figure 13.17.

If the access size exceeds the set bus width, burst access is performed. In a 32-byte burst transfer

(cache fill), the first access comprises a longword that includes the data requiring access. The

remaining accesses are performed on 32-byte boundary data that includes the relevant data. In

burst transfer (cache write-back), wraparound writing is performed for 32-byte data.

(SA: IO ← memory)

(SA: IO → memory)

Figure 13.17 DRAM Burst Access Timing

Rev. 4.0, 04/00, page 339 of 850

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