Hitachi SH7750 series Hardware Manual page 789

TRp1
CKIO
t
AD
BANK
Precharge-sel
Addr
t
RWD
RD/
t
RASD
t
CASD2
t
DQMD
DQMn
t
WDD
D63–D0
(write)
CKE
t
DACD
DACKn
Figure 23.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register
TRp2 TRp3 TRp4
t
CASD2
(High)
Setting (SET)
TMw TMw2 TMw3
t
AD
t t
CSD CSD
t
RWD
t
RASD
t
CASD2
Rev. 4.0, 04/00, page 781 of 850
TMw4 TMw5
t
AD
t
CSD
t
RWD
t
RASD
t
CASD2
t
DQMD
t
WDD
t
BSD
t
DACD