Hitachi SH7750 series Hardware Manual page 731

Table 22.1 Pin Functions (cont)
Pin
No. No. Pin Name
225 D8 A1
226 A8 STATUS0
227 B8 STATUS1
228 A7 MD6/
,2,649
229 C9 VDDQ
230 D9 VSSQ
$6(%5./
231 B7
BRKACK
232 A6 TDO
233 C7 VDD
234 D7 VSS
235 B6 TMS
236 A5 TCK
237 B5 TDI
7567
238 C4
&.,25(1% I
239 C3
240 C6 NC
241 A4 VDD-PLL2
242 D6 VSS-PLL2
243 B4 VDD-PLL1
244 D5 VSS-PLL1
245 A3 VDD-CPG
246 B3 VSS-CPG
247 A2 XTAL
I/O Function
O Address
O Status
O Status
I Mode/,2,649
(PCMCIA)
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O Pin break/
acknowledge
(H-UDI)
O Data out
(H-UDI)
Power Internal VDD
(1.8 V)
Power Internal GND
(0 V)
I Mode
(H-UDI)
I Clock
(H-UDI)
I Data in
(H-UDI)
I Reset
(H-UDI)
CKIO2, 5'5,
RD/:55
enable
Power PLL2 VDD
(3.3V)
Power PLL2 GND (0V)
Power PLL1 VDD
(3.3V)
Power PLL1 GND (0V)
Power CPG VDD
(3.3V)
Power CPG GND (0V)
O Crystal
resonator
SRAM DRAM
Reset
MD6
Memory Interface
SDRAM PCMCIA MPX
,2,649
Rev. 4.0, 04/00, page 723 of 850