Hitachi SH7750 series Hardware Manual page 787

TRs1
CKIO
t
AD
BANK
Precharge-sel
Addr
t
CSD
t
RWD
RD/
t
RASD
t
CASD2
t
DQMD
DQMn
t
WDD
D63–D0
(write)
CKE
t
DACD
DACKn
Figure 23.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC = 1)
TRs2 TRs3 TRs4
t
CSD
t
CSD
t
RASD
t
RASD
t
CASD2
t
CASD2
t
CKED
Trc
TRs5 Trc
t
CKED
Rev. 4.0, 04/00, page 779 of 850
Trc
t
AD
t
CSD
t
RWD
t
RASD
t
CASD2
t
DQMD
t
WDD
t
BSD
t
DACD