Hitachi SH7750 series Hardware Manual page 543

Superh risc engine
Hide thumbs Also See for SH7750 series:
Table of Contents

Advertisement

Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection
SCSMR1 Settings
Bit 7:
Bit 6:
Bit 2:
C/$ $ $ $
CHR
MP
0
0
0
1
0
1
1
1
*
*
Note: An asterisk in the table means "Don't care."
Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection
SCSMR1
SCSCR1 Setting
Bit 7:
Bit 1:
C/$ $ $ $
CKE1
0
0
1
1
0
1
Rev. 4.0, 04/00, page 532 of 850
Bit 5:
Bit 3:
PE
STOP Mode
0
0
Asynchronous
mode
1
1
0
1
0
0
1
1
0
1
0
Asynchronous
*
mode
1
(multiprocessor
0
format)
1
Synchronous
*
*
mode
Bit 0:
CKE0
Mode
0
Asynchronous
mode
1
0
1
0
Synchronous
mode
1
0
1
SCI Transfer Format
Multi-
Data
processor
Length
Bit
8-bit data
No
7-bit data
8-bit data
Yes
7-bit data
8-bit data
No
SCI Transmit/Receive Clock
Clock
Source
SCK Pin Function
Internal
SCI does not use SCK pin
Outputs clock with same
frequency as bit rate
External
Inputs clock with frequency of
16 times the bit rate
Internal
Outputs serial clock
External
Inputs serial clock
Parity
Stop Bit
Bit
Length
No
1 bit
2 bits
Yes
1 bit
2 bits
No
1 bit
2 bits
Yes
1 bit
2 bits
No
1 bit
2 bits
1 bit
2 bits
None

Advertisement

Table of Contents
loading

This manual is also suitable for:

Sh7750sSh7750

Table of Contents