Register Configuration - Hitachi SH7750 series Hardware Manual

12.1.4

Register Configuration

Table 12.2 summarizes the TMU registers.
Table 12.2 TMU Registers
Chan- Abbre-
nel Name viation R/W
Com- Timer TOCR
mon output
control
register
Timer TSTR
start
register
0 Timer TCOR0 R/W Ini-
constant
register 0
Timer TCNT0 R/W Ini-
counter 0
Timer TCR0
control
register 0
1 Timer TCOR1 R/W Ini-
constant
register 1
Timer TCNT1 R/W Ini-
counter 1
Timer TCR1
control
register 1
2 Timer TCOR2 R/W Ini-
constant
register 2
Timer TCNT2 R/W Ini-
counter 2
Timer TCR2
control
register 2
Input TCPR2 R
capture
register
Notes: 1. Not initialized in module standby mode when the input clock is the on-chip RTC output
clock.
2. Counts in module standby mode when the input clock is the on-chip RTC output clock.
Initialization
Power-
On Manual
Reset Reset
R/W Ini- Ini-
tialized tialized
R/W Ini- Ini-
tialized tialized
Ini-
tialized tialized
Ini-
tialized tialized
R/W Ini- Ini-
tialized tialized
Ini-
tialized tialized
Ini-
tialized tialized
R/W Ini- Ini-
tialized tialized
Ini-
tialized tialized
Ini-
tialized tialized
R/W Ini- Ini-
tialized tialized
Held Held
Stand-
by
Mode Initial Value P4 Address
Held H'00
Ini- H'00
1
tialized*
Held H'FFFFFFFF H'FFD80008 H'1FD80008 32
2
Held* H'FFFFFFFF H'FFD8000C H'1FD8000C 32
Held H'0000
Held H'FFFFFFFF H'FFD80014 H'1FD80014 32
2
Held* H'FFFFFFFF H'FFD80018 H'1FD80018 32
Held H'0000
Held H'FFFFFFFF H'FFD80020 H'1FD80020 32
2
Held* H'FFFFFFFF H'FFD80024 H'1FD80024 32
Held H'0000
Held Undefined
Area 7
Address
H'FFD80000 H'1FD80000 8
H'FFD80004 H'1FD80004 8
H'FFD80010 H'1FD80010 16
H'FFD8001C H'1FD8001C 16
H'FFD80028 H'1FD80028 16
H'FFD8002C H'1FD8002C 32
Rev. 4.0, 04/00, page 243 of 850
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