Hitachi SH7750 series Hardware Manual page 638

Superh risc engine
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Initialization
Clear TE and RE bits
in SCSCR1 to 0
Clear FER/ERS, PER, and
ORER flags in SCSCR1 to 0
In SCSMR1, set parity in O/ bit,
clock in CKS1 and CKS0 bits,
and set GM
Set SMIF, SDIR, and SINV bits
in SCSCMR1
Set value in SCBRR1
In SCSCR1, set clock in CKE1
and CKE0 bits, and clear TIE,
RIE, TE, RE, MPIE, and
TEIE bits to 0.
1-bit interval elapsed?
Set TIE, RIE, TE, and RE bits
in SCSCR1
End
Figure 17.7 Sample Initialization Flowchart
1
2
3
4
5
6
Wait
No
Yes
7
Rev. 4.0, 04/00, page 627 of 850

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