Hitachi SH7750 series Hardware Manual page 813

Figure 23.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address
TS1
CKIO
t
AD
A25–A0
t
CSD
t
RWD
RD/
t
RSD
D63–D0
(read)
t
WED1
t
BSD
t
DACD
DACKn
(SA: IO ← memory)
t
DACD
DACKn
(DA)
Setup/Hold Time Insertion, AnS = 1, AnH = 1)
T1 T2 TH1
t
RSD
t t
RDS RDH
t
WEDF
t
BSD
t
DACD
Rev. 4.0, 04/00, page 805 of 850
t
AD
t
CSD
t
RWD
t
RSD
t
WED1
t
DACD