Hitachi SH7750 series Hardware Manual page 347

Address Multiplexing: When area 2 or area 3 is designated as DRAM space, address
multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row
and column address multiplexing, to be connected to the SH7750 Series without using an external
address multiplexer circuit. Any of the five multiplexing methods shown below can be selected,
by setting bits AMXEXT and AMX2–0 in MCR for area 2 or 3 DRAM. The relationship between
the AMXEXT and AMX2–0 bits and address multiplexing is shown in table 13.14. The address
output pins subject to address multiplexing are A17 to A1. The address signals output by pins A25
to A18 are undefined.
Table 13.14 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing
Setting
AMXEXT AMX2 AMX1
0 0 0
1
1 0
Other settings
Rev. 4.0, 04/00, page 336 of 850
Number
of Column
Address
AMX0 Bits Output Timing
0 8 bits Column address
Row address
1 9 bits Column address
Row address
0 10 bits Column address
Row address
1 11 bits Column address
Row address
0 12 bits Column address
Row address
Reserved —
External Address Pins
A1–A13 A14 A15
A1–A13 A14 A15
A9–A21 A22 A23
A1–A13 A14 A15
A10–A22 A23 A24
A1–A13 A14 A15
A11–A23 A24 A25
A1–A13 A14 A15
A12–A24 A25 A15
A1–A13 A14 A15
A13–A25 A14 A15
— — —
A16 A17
A16 A17
A24 A25
A16 A17
A25 A17
A16 A17
A16 A17
A16 A17
A16 A17
A16 A17
A16 A17
— —