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13.1.4
Register Configuration
The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode
register incorporated in synchronous DRAM can also be accessed as an SH7750 Series register.
The functions of these registers include control of interfaces to various types of memory, wait
states, and refreshing.
Table 13.2 BSC Registers
Name
Bus control register 1
Bus control register 2
Wait state control
register 1
Wait state control
register 2
Wait state control
register 3
Memory control register MCR
PCMCIA control register PCR
Refresh timer
control/status register
Refresh timer counter
Refresh time constant
counter
Refresh count register
Synchronous
For
DRAM mode
area 2
registers
For
area 3
Note: * For details, see section 13.2.8, Synchronous DRAM Mode Registers.
Rev. 4.0, 04/00, page 264 of 850
Abbrevia-
R/W
tion
BCR1
R/W
BCR2
R/W
WCR1
R/W
WCR2
R/W
WCR3
R/W
R/W
R/W
RTCSR
R/W
RTCNT
R/W
RTCOR
R/W
RFCR
R/W
SDMR2
W
SDMR3
Initial
P4
Value
Address
H'0000 0000 H'FF80 0000 H'1F80 0000 32
H'3FFC
H'FF80 0004 H'1F80 0004 16
H'7777 7777 H'FF80 0008 H'1F80 0008 32
H'FFFE EFFF H'FF80 000C H'1F80 000C 32
H'0777 7777 H'FF80 0010 H'1F80 0010 32
H'0000 0000 H'FF80 0014 H'1F80 0014 32
H'0000
H'FF80 0018 H'1F80 0018 16
H'0000
H'FF80 001C H'1F80 001C 16
H'0000
H'FF80 0020 H'1F80 0020 16
H'0000
H'FF80 0024 H'1F80 0024 16
H'0000
H'FF80 0028 H'1F80 0028 16
—
H'FF90 xxxx* H'1F90 xxxx
H'FF94 xxxx* H'1F94 xxxx
Area 7
Access
Address
Size
8
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