Hitachi SH7750 series Hardware Manual page 355

Superh risc engine
Hide thumbs Also See for SH7750 series:
Table of Contents

Advertisement

CKIO
A25–A0
RD/
D63–D0
(read)
DACKn
(SA: IO ← memory)
Figure 13.20 (3) DRAM Burst Bus Cycle, RAS Down Mode Start
Rev. 4.0, 04/00, page 344 of 850
Tpc
Tr1
Tr2
Tc1
r
(EDO Mode, RCD = 0, Anw = 0)
Tc2
Tc1
Tc2
c1
c2
d1
Tc1
Tc2
Tc1
Tc2
c3
d2
d3
Tce
c4
d4

Advertisement

Table of Contents
loading

This manual is also suitable for:

Sh7750sSh7750

Table of Contents