Starting The Flash Memory Automatic Algorithm - Fujitsu MB90390 Series Hardware Manual

Table of Contents

Advertisement

28.5

Starting the Flash Memory Automatic Algorithm

Four types of commands are available for starting the flash memory automatic
algorithm: Read/Reset, Write, and Chip Erase. Control of suspend and restart is enabled
for sector erase.
■ Command Sequence Table
Table 28.5-1 lists the command sequence table. All of the data written to the command register is in bytes,
but use word access to write. The data of the high-order bytes at this time is ignored.
Table 28.5-1 Command Sequence Table
1st bus write
Bus
Command
write
sequence
access
Address
*
1
FxXXXX
Read/Reset
*
4
FxAAAA
Read/Reset
Write program
4
FxAAAA
Chip Erase
6
FxAAAA
Sector Erase
6
FxAAAA
Sector Erase Suspend
Sector Erase Restart
Auto-select
3
FxAAAA
*: Both of the two types of Read/Reset commands can reset the flash memory to read mode.
Notes:
• The addresses Fx in the table mean FF, FE, FD, FB, FA and F9 for 3M-bit Flash Memory. Use
these addresses as the access target bank values for operations.
• The addresses in the table are the values in the CPU memory map. All addresses and data are
represented using hexadecimal notation. However, the letter "X" is an optional value.
• RA: Read address
• PA: Write address. Only even addresses can be specified.
• SA: Sector address. See Section "28.2 Block Diagram of the Entire Flash Memory and Sector
Configuration of the Flash Memory".
• RD: Read data
• PD: Write data. Only word data can be specified.
2nd bus write cycle
cycle
Data
Address
Data
XXF0
-
-
XXAA
Fx5554
XX55
XXAA
Fx5554
XX55
XXAA
Fx5554
XX55
XXAA
Fx5554
XX55
Entering address FxXXXX data (xxB0H) suspends erasing during sector erase.
Entering address FxXXXX data (xx30H) restarts erasing after erasing is suspended during sector erase.
XXAA
Fx5554
XX55
CHAPTER 28 3M-BIT FLASH MEMORY
3rd bus write cycle
4th bus write cycle
Address
Data
Address
-
-
-
FxAAAA
XXF0
RA
PA
FxAAAA
XXA0
(even)
FxAAAA
XX80
FxAAAA
FxAAAA
XX80
FxAAAA
FxAAAA
XX90
-
5th bus write cycle
6th bus write cycle
Data
Address
Data
Address
-
-
-
RD
-
-
PD
-
-
(word)
XXAA
Fx5554
XX55
FxAAAA
XXAA
Fx5554
XX55
(even)
-
-
-
Data
-
-
-
-
-
-
XX10
SA
XX30
-
-
563

Advertisement

Table of Contents
loading

Table of Contents