Message Buffers - Fujitsu MB90390 Series Hardware Manual

23.6.20

Message Buffers

There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register
(IDRx), DLC register (DLCRx), and data register (DTRx).
■ Message Buffers
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The message buffer (x) is used both for transmission and reception.
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The lower-numbered message buffers are assigned higher priority.
• At transmission, when a request for transmission is made to more than one message buffer, transmission
is performed, starting with the lowest-numbered message buffer (See Section "23.7 Transmission of
CAN Controller").
• At reception, when the received message ID passes through the acceptance filter (mechanism for
comparing the acceptance-masked ID of received message and message buffer) of more than one
message buffer, the received message is stored in the lowest-numbered message buffer (See Section
"23.8 Reception of CAN Controller").
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When the same acceptance filter is set in more than one message buffer, the message buffers can be
used as a multi-level message buffer. This provides allowance for receiving time.
(See Section "23.12 Procedure for Reception by Message Buffer (x)").
Notes:
• A write operation to message buffers and general-purpose RAM areas should be performed in
words to even addresses only. A write operation in bytes causes undefined data to be written to
the upper byte at writing to the lower byte. Writing to the upper byte is ignored.
• When the BVALx bit of the message buffer valid register (BVALR) is "0" (Invalid), the message
buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM.
During the receive/transmit operation of the CAN controller, the CAN Controller write/read to/from
the message buffers. If the CPU tries to write/read to/from the message buffers in this period, the
CPU has to wait a maximum time of 64 machine cycles.
This is also true for the general-purpose RAM.
CHAPTER 23 CAN CONTROLLER
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