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CHAPTER 21 400 kHz I
21.2.3
Ten Bit Slave Address Register (ITBA)
This register (ITBAH / ITBAL) designates the ten bit slave address.
■ Ten Bit Slave Address Register (ITBA)
Write access to this register is only possible if the interface is disabled (EN= 0 in ICCR).
R/
W
:
Readable and writable
-
:
Undefined
■ Ten Bit Slave Address Register (ITBA) Contents
Table 21.2-3 Function of Each Bit of the Ten Bit Slave Address Register (ITBA)
Bit name
bit15 to
Undefined
bit10
TA9 to TA0:
bit9 to bit0
Ten bit slave
address
Notes:
• A ten bit header (write access) consists of the following bit sequence: 11110
• A ten bit header (read access) consists of the following bit sequence: 11110
422
2
C INTERFACE
bit
15
14
13
12
Address:
0035A3
H
-
-
-
-
-
-
bit
7
6
5
Address:
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0
0035A2
H
R/W R/W R/W R/W
These bits always return "0".
When address data is received in slave mode, it is compared to the ITBA register if
the ten bit address is enabled (ENTB = 1 in the ITMK register). An acknowledge is
sent to the master after reception of a ten bit address header with write access1. Then,
the second incoming byte is compared to the TBAL register. If a match is detected,
an acknowledge signal is sent to the master device and the AAS bit is set.
Additionally, the interface acknowledges upon the reception of a ten bit header with
read access2 after a repeated start condition.
All bits of the slave address may be masked using the ITMK register. The received
ten bit slave address is written back to the ITBA register, it is only valid while the
AAS bit in the IBSR register is "1".
11
10
9
8
ITBAH (upper)
-
-
-
TA9 TA8
Initial value
0 0 0 0 0 0 0 0
-
-
-
R/W R/W
4
3
2
1
0
ITBAL (lower)
Initial value
0 0 0 0 0 0 0 0
R/W
R/W
R/W R/W
Function
B
B
, TA9, TA8, 0.
B
, TA9, TA8, 1.
B
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