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CHAPTER 20 UART2, UART3
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LIN Synch Break Detection Interrupt and Flags
If a LIN Synch synchronization break is detected in the slave mode, the LIN Break Detected (LBD) Flag of
the ESCR2/ESCR3 is set to "1". This causes an interrupt, if the LIN Break Interrupt Enable (LBIE) bit is
set.
Serial clock
cycle#
Serial
clock
Serial
Input
(LIN bus)
FRE
(RXE=1)
LBD
(RXE=0)
The figure above demonstrates the LIN synch break detection and flag set timing.
Note, that if reception is enabled (RXE = 1) and reception interrupt is enabled (RIE = 1) the Reception Data
Framing Error (FRE) flag bit of the SSR2/SSR3 will cause a reception interrupt 2 bit times ("8N1") earlier
than the LIN break interrupt, so it is recommended to turn off RXE, if a LIN break is expected.
MB90V390H/MB90F394H(A):
LBD is only supported in operation mode 0 and 3. Upon LIN break detection, the reception error flags
(SSR2/SSR3:FRE, SSR2/SSR3:ORE, SSR2/SSR3:PE) and the reception data register full flag (SSR2/
SSR3:RDRF) are cleared.
MB90V390HA/MB90V390HB/MB90394HA:
LBD is only supported in operation mode 3. Upon LIN break detection, the reception error flags (SSR2/
SSR3:FRE, SSR2/SSR3:ORE, SSR2/SSR3:PE) and the reception data register full flag (SSR2/
SSR3:RDRF) are not cleared.
Figure 20.7-8 shows a typical start of a LIN message frame and the behavior of the UART2, UART3.
Serial
clock
Serial
Input
(LIN bus)
LBD
Internal
ICU
Signal
390
Figure 20.7-7 LIN Synch Break Detection and Flag Set Timing
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reception interrupt occurs, if RXE=1
Figure 20.7-8 UART2, UART3 Behavior as Slave in LIN Mode
Synch break
(e. g. 14 bit)
Reception interrupt occurs, if RXE=0
LBR cleared
by CPU
Synch field
MB90V390HA/
MB90V390HB/
MB90394HA
MB90V390H/
MB90F394H(A)
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