Fujitsu MB90390 Series Hardware Manual page 213

■ Watchdog Timer Control Register (WDTC)
Figure 12.1-2 Configuration of Watchdog Timer Control Register (WDTC)
Address :
0000A8
H
R : Read only
W : Write only
X : Undefined value
- : Undefined
[bit7, bit5 to bit3] PONR, WRST, ERST, and SRST
These flags indicate the reset causes. The flags are set upon a reset as described in Table 12.1-1.
All bits are cleared to "0" after the WDTC register is read. These bits are read-only bits.
Table 12.1-1 Reset Cause Registers
*: The previous value is maintained.
[bit2] WTE
While the watchdog timer is stopped, writing "0" to this bit activates the watchdog timer. Subsequently,
writing "0" clears the watchdog timer counter. Writing "1" has no effect.
The watchdog timer is stopped by power-on or reset by watchdog timer. "1" is always read from this
bit.
bit7 bit6 bit5
PONR - WRST ERST SRST
R - R
Reset cause
Power-on
Watchdog timer
External pin
RST bit
bit4 bit3 bit2
WTE WT1
R R W
PONR WRST
1 -
* 1
* *
* *
CHAPTER 12 WATCHDOG TIMER
Initial value
bit1 bit0
XXXXX111
WT0
W W
ERST SRST
- -
* *
1 *
* 1
B
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