Table of Contents
Advertisement
16.3.1
PPG0 Operation Mode Control Register (PPGC0)
PPGC0 is a five-bit control register that selects the operation mode of the block,
controls pin outputs, selects count clock, and controls triggers.
■ PPG0 Operation Mode Control Register (PPGC0)
Figure 16.3-1 Configuration of the PPG0 Operation Mode Control Register
PPG0 operation mode control register
bit
Address:
ch.0, 000038
H
PEN0
Read/write
(R/W)
Initial value
(0)
Other ch.:
ch.2 00003C
H
ch.4 000040
H
ch.6 000044
H
ch.8 000048
H
ch.A 00004C
H
R/W
:
Readable and writable
X
:
Undefined value
-
:
Undefined
:
Initial value
7
6
5
4
-
PE00
PIE0
PUF0
(-)
(R/W)
(R/W)
(R/W)
(X)
(0)
(0)
(0)
3
2
1
0
PPGC0
-
-
Reserved
(-)
(-)
(W)
(X)
(X)
(1)
bit 0
Reserved
1
bit 3
PUF0
0
1
bit 4
PIE0
0
1
bit 5
PE00
0
1
bit 7
PEN0
0
1
CHAPTER 16 8/16-BIT PPG
Reserved bit
When setting PPGC0, always set this bit to "1".
PPG counter underflow bit
PPG counter underflow is not detected.
PPG counter underflow is detected.
PPG interrupt enable bit
Interrupt disabled.
Interrupt enabled.
PPG00 pin output enable bit
Pulse output disabled (general-purpose port).
Pulse output enabled.
Operation enable bit
Stop ( "L" level output maintained).
PPG operation enabled.
255
Advertisement
Table of Contents
